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989 IP
601
0.118
UMC 55nm eHV process;Single-Port SRAM compiler
UMC 55nm eHV process;Single-Port SRAM compiler...
602
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
603
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT periphery high density single port SR...
604
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler with row redundancy.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
605
0.118
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single port SRAM memory compiler.
UMC 55nm embedded flash and embedded E2PROM ultra low power split-gate process synchronous well bias feature HVT+uHVT periphery high density single po...
606
0.118
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 55nm Embedded Flash and Embedded E2PROM Ultra Low Power Split-Gate Process...
607
0.118
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power split-gate via 1 ROM compiler with well bias...
608
0.118
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias
UMC 55nm embedded flash and embedded e2prom ultra low power splite-gate synchronous via1 rom complier with well bias...
609
0.118
UMC 55nm Logic process standard synchronous Contact ROM memory compiler.
UMC 55nm Logic process standard synchronous Contact ROM memory compiler....
610
0.118
UMC 55nm Logic process standard synchronous Contact ROM memory compiler.
UMC 55nm Logic process standard synchronous Contact ROM memory compiler....
611
0.118
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler.
UMC 55nm Low-K/Low-Power Logic process synchronous ultra-high-speed single-port SRAM compiler....
612
0.118
UMC 55nm LP process with PG Dual port SRAM compiler
UMC 55nm LP process with PG Dual port SRAM compiler...
613
0.118
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST process standard synchronous high density single port SRAM memory compiler....
614
0.118
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler.
UMC 55nm SST/ulp Logic process standard synchronous high density single port SRAM memory compiler....
615
0.118
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File
UMC 55nm Standard Performance LowK Logic Process Two-Port Register File...
616
0.118
UMC 55nm ULP Low-K process HVT via1 ROM
UMC 55nm ULP Low-K process HVT via1 ROM...
617
0.118
UMC 55nm ULP Low-K process One Port Register File for periphery HVT
UMC 55nm ULP Low-K process One Port Register File for periphery HVT...
618
0.118
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT
UMC 55nm ULP Low-K process, Single-Port SRAM with Row repair & periphery HVT...
619
0.118
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery
UMC 55nm uLP LowK Logic Process One Port Register File with forward biased and UHVT periphery...
620
0.118
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT
UMC 55nm uLP LowK Logic Process One Port Register File with well bias & periphery HVT...
621
0.118
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...
622
0.118
UMC 55nm ULP process PG-One Port Register File for periphery HVT
UMC 55nm ULP process PG-One Port Register File for periphery HVT...
623
0.118
UMC 55nm ULP process ROM compiler with HVT peripheral
UMC 55nm ULP process ROM compiler with HVT peripheral...
624
0.118
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT
UMC 55nm ULP-SST process PG One Port Register File for periphery HVT...
625
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
626
0.118
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler.
UMC 55nm ULP-SST process standard synchronous high density single port SRAM memory compiler....
627
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
628
0.118
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM...
629
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with RED Well Biase Memory compiler...
630
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias & RED Memory Compiler...
631
0.118
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler
UMC 55nm ULP/LowK Process Single-Port SRAM with well bias HVT Memory Compiler...
632
0.118
UMC 55nm ULP/LowK Process via ROM compiler for well bias
UMC 55nm ULP/LowK Process via ROM compiler for well bias...
633
0.118
UMC 55nm ULP/LowK Process via1 ROM compiler well bias
UMC 55nm ULP/LowK Process via1 ROM compiler well bias...
634
0.118
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT
UMC 55nm ULP/LowK Single-Port SRAM with Well Bias uHVT...
635
0.118
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.
UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler....
636
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy....
637
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
638
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
639
0.118
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler....
640
0.118
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler_x005F_x005F_x005F_x005F_x005F_x000D_
UMC 80nm HV Process PG Single-Port SRAM Memory Compiler...
641
0.118
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy
UMC 80nm HV Process Single-Port SRAM Memory Compiler with redundancy...
642
0.118
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler
UMC 80nm LL/eHV Process synchronous Via ROM memory compiler...
643
0.118
UMC 90nm SPLVT ultra-high speed 1-port SRAM
UMC 90nm SPLVT ultra-high speed 1-port SRAM...
644
0.118
UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler
UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler...
645
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process
UMC 55um LP Low-K process One Port Register File compiler....
646
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), UMC 55nm LP process
UMC 55nm LP Logic process 0.425um2-Bit cell One Port Register File memory compiler....
647
0.118
One Port Register File Compiler IP, HJTC 0.18um pFlash process
HJTC 0.18um pFlash process synchronous Single Port Register File memory compiler....
648
0.118
One Port Register File Compiler IP, UMC 0.11um CIS process
UMC 0.11um CMOS Image Sensor 2P3M process synchronous high density Single Port Register File SRAM memory compiler....
649
0.118
One Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Advanced Enhancement) Logic process 1.41um2 cell One Port Register File memory compiler....
650
0.118
One Port Register File Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um AE eFlash HS process for One Port Register File compiler....